The conventional circuit for input buffer for CMOS technology is based on conventional CMOS inverters, as presented in FIG. 2. In that circuit, NMOS transistor NC1 and PMOS transistor PC1 (as show in FIG. 2) act as input stage inverter, which is powered by VDDH supply (node 83 in FIG. 2), and provides output voltage levels of VDDH and GNDH (node 85 in FIG. 2). The second stage is a CMOS inverter, constructed by NMOS transistor NC2 and PMOS transistor PC2 (as show in FIG. 2), powered by VDDL supply (node 84 on FIG. 2), which is typically the same or lower voltage than VDDH. VDDL is typically equal to the core voltage of the integrated circuit. The input signal to this circuit is names VIN (node 80 on FIG. 2), and the output signal is named VOUT (node 82 on FIG. 2).
The circuit in FIG. 2 has several disadvantages, which are:    1. The supply current when VIN is higher than GNDH, or lower than VDDH is relatively high due to the short circuit between PC1 and NC1 transistors which are both open, consuming a significant amount of power. In applications that requires low power consumption, this is a significant drawback.    2. The current between VDDH to GNDH during transition of VIN is relatively high, since both NC1 and PC1 have gate to source voltage that exceeds their threshold levels. This current is called short circuit current between PC1 and NC1, in which both transistors are conducting. This effect causes a significant consumption of current, especially when VDDH is high and when input transition time is long. In applications that requires low power consumption, this is a significant drawback.    3. When VDDL is very low, typically when VDDL<Vtn+|Vtp| (Vtn is the threshold voltage of the NMOS transistor; Vtp is the threshold voltage of the PMOS transistor), the transition time and the delay time on the output of the first inverter (node 81 in FIG. 2) are very high. This fact increases the delay of this cell, and might cause the second inverter to consume high short circuit current. This is a significant drawback when core voltage is very low, such as in the case of ultra-low power applications.    4. When the voltage of VDDH is significantly higher than VDDL, the difference between the delay when VIN is rising, relative to the delay when VIN is falling, is high. This asymmetric delay might cause timing issues in the integrated circuit.
U.S. Pat. No. 4,958,088 describes a CMOS input buffer with hysteresis, but it does not reduce the current due to non-full swing input signal, and output level is the same as input level.
U.S. Pat. No. 5,304,867 describes a high speed and low power CMOS input buffer. It is intended for TTL input signal levels, and does not have the mechanism for reducing the supply current when VIN is slightly above GNDH. In addition, output voltage levels are the same as input voltage levels.